A Polymorphic Register File Architecture
نویسندگان
چکیده
Previous vector architectures divided the available register file space in a fixed number of registers of equal sizes. We propose a novel register file organization which allows dynamic creation of a variable number of multidimensional registers of arbitrary sizes the Polymorphic Register File. We have selected Floyd 64x64 as our benchmark. Simulation results suggest a speedup of up to 8X compared to an idealized Cell PPU scalar processor and a large reduction in the number of executed instructions. Preliminary results indicate that the proposed architecture outperforms the Cell SPU by around 50% without exceeding the 256KB storage size of the Local Store.
منابع مشابه
Scalability Evaluation of a Polymorphic Register File: A CG Case Study
We evaluate the scalability of a Polymorphic Register File using the Conjugate Gradient method as a case study. We focus on a heterogeneous multi-processor architecture, taking into consideration critical parameters such as cache bandwidth and memory latency. We compare the performance of 256 Polymorphic Register File-augmented workers against a single Cell PowerPC Processor Unit (PPU). In such...
متن کاملA Configurable Multi-ported Register File Architecture for Soft Processor Cores
This paper describes the architecture of a configurable, multiported register file for soft processor cores. The register file is designed using the low-latency block RAMs found in high-density FPGAs like the Xilinx Virtex-4. The latency of the register file and its utilization of FPGA resources are evaluated with respect to design parameters that include word length, register file size, and nu...
متن کاملOptimizing Instruction Scheduling and Register Allocation for Register-File-Connected Clustered VLIW Architectures
Clustering has become a common trend in very long instruction words (VLIW) architecture to solve the problem of area, energy consumption, and design complexity. Register-file-connected clustered (RFCC) VLIW architecture uses the mechanism of global register file to accomplish the inter-cluster data communications, thus eliminating the performance and energy consumption penalty caused by explici...
متن کاملScalable Distributed Register File
In microarchitectural design, conceptual simplicity does not always lead to reduced technological complexity. VLSI design offers several standard structures which get very inefficient when they are scaled up. For instance, the superscalar OOO processing model is conceptually simple – with the controlflow oriented front-end and the dataflow oriented backend – but simply scaling the structures in...
متن کامل